PIC1. 6F8. 77 CCP Modules Capture Compare PWM Modes. RELATED ARTICLES TAKE A LOOK INTRODUCTION TO PIC 1. F8. 77. TAKE A LOOK PIC 1. F8. 77 ARCHITECTURE AND MEMORY ORGANIZATIONTAKE A LOOK REGISTER MEMORY ORGANIZATION IN PIC 1. F8. 77. TAKE A LOOK TIMER MODULES IN PIC 1. F8. 77. Capture Compare Pulse Width Module CCP is a special module designs for modulation and waveform generation applications. This module basically works on three different modes capturecompare and PWM odes. Capture The Flag Review' title='Capture The Flag Review' />Its great to see so many shooters making their mark on the industry again. I mean, they never really left, because right after Unreal Tournament stopped being. The PIC 1. 6F8. 77 chip contains two CCP ports CCP1 and CCP2. Each of this CCP module contains 1. Unfortunately for Chris, hes been captured by some bad men. Fortunately for you, its time to take advantage of him Specifically for gay audiences but. Capture register 1. Compare register PWM MasterSlave Duty Cycle registers. The CCP1 and CCP2 modules are identical in its operation except in its special event trigger operation. In each CCP modules, the capture, compare and PWM modes using different timer resources. The table below shows the different CCP modes and its timer resources. The detailed explanations and functions of CCP module is given below. CCP1 Module. CaptureComparePWM Register 1 CCPR1 is a 1. CCPR1. L low byte and CCPR1. H high byte. The CCP1. CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer. Download Divx Cinderella 3D Cartoon. CCP2 Module. CaptureComparePWM Register 2 CCPR2 is comprised of two 8 bit registers CCPR2. L low byte and CCPR2. H high byte. The CCP2. CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer. AD conversion if the AD module is enabled. Capture Mode. In Capture mode, CCPR1. H CCPR1. L captures the 1. TMR1 register when an event occurs on pin RC2CCP1. An event is defined as one of the following Every falling edge Every rising edge Every 4th rising edge Every 1. The type of event is configured by control bits, CCP1. M3 CCP1. M0 CCPx. CONlt 3 0. When a capture is made, the interrupt request flag bit, CCP1. IF PIR1lt 2, is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new value. The block diagram of capture mode is shown below. Compare Mode. In Compare mode, the 1. CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2CCP1 pin is Driven high Driven low Remains unchanged. The action on the pin is based on the value of control bits, CCP1. M3 CCP1. M0 CCP1. CONlt 3 0. At the same time, interrupt flag bit CCP1. IF is set. The compare mode block diagram is shown below. PWM Mode PWMIn Pulse Width Modulation mode, the CCPx pin produces up to a 1. PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISClt 2 bit must be cleared to make the CCP1 pin an output. Figure shows a simplified block diagram of the CCP module in PWM mode. Setup for PWM Operation. The following steps should be taken when configuring the CCP module for PWM operation 1. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1. L register and CCP1. CONlt 5 4 bits. Make the CCP1 pin an output by clearing the TRISClt 2 bit. Set the TMR2 prescale value and enable Timer. T2. CON. 5. Configure the CCP1 module for PWM operation. The table below shows PWM FREQUENCIES and RESOLUTIONS AT 2. MHz and registers associated with CCP timer. To know more about PIC, click on the link below. TAKE A LOOK USART MODULES IN PIC 1.